OCR J277 Mark Scheme - The Fetch-Execute Cycle

OCR	GCSE (9-1) Computer Science Mark Scheme J277/01: The Fetch-Execute Cycle

Question	Answer	Marks	Guidance
1a	Fetch Decode Execute	3	Must be in correct order for full marks.
1b	Main Memory / Memory / RAM	1	Do not accept: "Hard Drive" or "Storage".
2	False (PC stores address, not instruction) True True True	4	1 mark per correct tick.
3	PC: Stores the address of the next instruction to be fetched. Increments each cycle. MAR: Stores the address of the location in memory where data/instructions are to be fetched or written. MDR: Stores the instruction/data that has just been fetched from, or is about to be written to, memory. ACC: Stores the result of calculations/processing from the ALU.	4	Examiner's Note: Ensure candidates specify "Address" for MAR and "Data/Instruction" for MDR. Vague answers like "Stores info" get 0 marks.
4	The PC stores an address / memory location. (1) It stores the address of the next instruction to be fetched, not a count of programs. (1)	2	Must correct the misconception about "counting programs".
5	Indicative Content: The PC holds the address of the next instruction. The MAR holds the memory address of the instruction/data to be fetched. The MDR holds the instruction/data that has been fetched from memory. The PC is incremented (to point to the next instruction). The instruction in the MDR is decoded by the Control Unit (CU). Marking Levels: Level 3 (5–6 marks): Detailed description including the correct transfer (PC -> MAR) and the incrementing of the PC. Level 2 (3–4 marks): Describes the fetch process but may miss a specific register step (e.g. omitting the copy to MAR). Level 1 (1–2 marks): Basic statement of "Fetch, Decode, Execute" without detail on registers.	6	Use a "best fit" approach to marking the levels.