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Cycle Frequency 0
Cycle Rank Idle Thread
1(a) [3 Marks]
The CPU continuously repeats a cycle to process data.
Identify the three stages of this cycle in the correct order.
💡Hint: First it gets instructions, then understands them, then runs them.
✅ Mark Scheme
  1. Fetch
  2. Decode
  3. Execute
⚠️ Important Must be in the correct order for full marks.
Score yourself (Max 3):
1(b) [1 Mark]
State the name of the component where instructions are fetched from during this cycle.
💡Hint: It's also known as RAM.
✅ Mark Scheme
  • Main Memory / Memory / RAM
⚠️ Examiner's Trap Do NOT accept "Hard Drive" or "Storage".
Did you get it right?
2 [4 Marks]
Tick one box in each row to show whether each statement about the Fetch-Execute cycle is True or False.
Statement Selection
The Program Counter (PC) stores the instruction currently being executed.
The cycle repeats continuously while the computer is turned on.
During the decode stage, the instruction is interpreted by the Control Unit.
The MAR stores the address of the instruction to be fetched.
✅ Mark Scheme
  1. False (PC stores the address, not the instruction)
  2. True
  3. True
  4. True
Score yourself (1 mark per correct row):
3 [4 Marks]
Complete the matching exercise by connecting each Register to its purpose in the Fetch-Execute Cycle.
💡Hint: "Address" Register stores addresses. "Data" Register stores instructions/data.
Program Counter (PC)
Memory Address Register (MAR)
Memory Data Register (MDR)
Accumulator (ACC)
Stores the instruction/data fetched from memory.
Stores the result of calculations/processing.
Stores the address of the next instruction to be fetched.
Stores the address of the instruction/data to be fetched.
✅ Mark Scheme
  • PC: Stores the address of the next instruction to be fetched.
  • MAR: Stores the address of the instruction/data to be fetched.
  • MDR: Stores the instruction/data fetched from memory.
  • ACC: Stores the result of calculations/processing.
⚠️ Examiner's Trap Ensure you specify "Address" for MAR and "Data/Instruction" for MDR. Vague answers get 0.
Score yourself (1 mark per correct match):
4 [2 Marks]
A student states: "The Program Counter (PC) counts how many programs have been run."
Explain why the student is incorrect.
💡Hint: What does the PC actually point to? It's not a program counter in that sense.
✅ Mark Scheme
  • The PC stores an address / memory location. (1)
  • It stores the address of the next instruction to be fetched, not a count of programs. (1)
Score yourself (Max 2):
5 [6 Marks]
Describe the events that take place during the Fetch and Decode stages of the cycle.
In your answer, you must refer to how the registers are used to transfer data.
💡Hint: Start with the PC. How are MAR and MDR used? Mention incrementing and decoding.
✅ Mark Scheme
Indicative Content:
  • The PC holds the address of the next instruction.
  • The MAR holds the memory address of the instruction/data to be fetched.
  • The MDR holds the instruction/data that has been fetched from memory.
  • The PC is incremented (to point to the next instruction).
  • The instruction in the MDR is decoded by the Control Unit (CU).

Marking Levels:
  • Level 3 (5–6 marks): Detailed description including PC -> MAR and PC increment.
  • Level 2 (3–4 marks): Describes fetch but may miss a specific register step.
  • Level 1 (1–2 marks): Basic statement without detail on registers.
Score yourself (Max 6):