Visual FDE Cycle Dashboard
Conceptually step through the CPU's primary task. Watch how instructions are retrieved from memory and processed internally.
Carries addresses and data between CPU & RAM.
Crucial: Stores the address of the NEXT instruction to fetch.
Crucial: Stores the address CURRENTLY being fetched from RAM.
Role: Safely holds the actual DATA or INSTRUCTION returned from RAM.
Role: Stores the temporary RESULT of calculations from the ALU.
Cycle Ready
The CPU is waiting to start the FDE cycle. Notice the Program Counter holds the starting memory address: 0x01.
Check Your Understanding
1. What is the fundamental difference in the roles of the PC and the MAR during the Fetch stage?
2. During the Decode stage, which component is responsible for interpreting the binary instruction in the MDR?
Written Exam Scenario (AO2/AO3)
Grade 9 Challenge"A developer argues that having separate MAR and MDR registers is unnecessary, and one single combined register should handle everything communicating with RAM. Explain why they are incorrect." (4 marks)
Simultaneous Operation: The MAR and MDR serve completely different roles that need to happen at the same time. The MAR (Memory Address Register) holds a location pointer, while the MDR (Memory Data Register) receives the incoming instruction from that location.
Logic Conflict: If there were only one register, placing an address in it to look up would be immediately overwritten by the data returning from RAM.
Control Precision: By keeping them separate, the CPU can safely maintain exactly where it is fetching from, while independently storing what it has fetched, ensuring instructions are retrieved sequentially without data corruption.